Porting of HDL Laboratory Experiences to Verilog

Hardware description languages, such as Verilog and VHDL, allow us to work with the design, behavior and operations of digital circuits. They are an essential skill for taking advantage of reconfigurable computing implementations, which can exhibit speedups of 100x over traditional processors for some applications.  An effective way of learning HDLs and reconfigurable technology is through well-designed programming and implementation exercises.  The goal of our project is to adapt the lab manual “VHDL Laboratory: Design of an Alarm Clock” by Dr. Manuel Jiménez, University of Puerto Rico - Mayagüez, to the Verilog programming language. The manual encourages the practice of HDL concepts through a series of five experiments to incrementally build an alarm clock: “Display Driver”, “The Time Block”, “The Alarm Clock”, “Snooze Function” and “Alarm Clock Integration”. We will discuss our adaptation of the experiments and didactic enhancements to the manual.